1. Field of the Invention
The present invention relates to control of word line activation in a semiconductor memory device.
2. Description of the Related Art
Commonly used semiconductor memory devices include DRAM and SRAM. It is common knowledge that while DRAM offers higher capacity at lower price than SRAM, it requires refresh operations. SRAM, on the other hand, while easier to use due to the lack of a need for refresh operations, is more expensive and has lower capacity than DRAM.
Virtual SRAM (known as VSRAM or PSRAM) is a semiconductor memory device that offers that advantages of both DRAM and SRAM. Virtual SRAM has a memory cell array composed of dynamic memory cells identical to those in DRAM, and also houses a refresh controller that allows refresh operations to be performed internally. Thus, external devices connected to virtual SRAM (such as a CPU) can access (i.e., read or write data) virtual SRAM without being aware of refresh operations. This feature of virtual SRAM is known as “refresh transparency.”
During each cycle in which virtual SRAM is accessed, the word line selected by an address must be activated and deactivated. However, in instances where, for example, the same word line is activated during consecutive cycles, repeated activation and deactivation of the word line during each cycle represents a waste of power. This problem is not limited to virtual SRAM, being common to all semiconductor memory devices in which word lines are repeatedly activated and deactivated in each cycle.